In the field of integrated circuits, active semiconductor devices such as, for example, transistors are generally manufactured or fabricated through processes commonly known as front end of line (FEOL) technologies. A transistor may be, for example, a field-effect-transistor (FET) and may be more specifically a complementary metal-oxide-semiconductor (CMOS) FET. Depending on the type of conduction, a FET may be a p-type dopant doped PFET or an n-type dopant doped NFET. A FET includes a source, drain and gate region. The FET may be planar or 3D (i.e. a FinFET).
Generally, after structure of a transistor is formed, conductive contacts comprising a silicide are formed to connect to source, drain, and/or gate of the transistor to circuitry that makes the transistor fully functional. With the continuous scaling down in device dimension in integrated circuits, real estate for forming corresponding contacts is also becoming smaller and smaller.
As device dimensions scale, silicide to source-drain resistance (interface resistivity divided by contact area) increases with the inverse of the source/drain contact width. Silicide to source-drain interface resistivity is determined by the interface doping concentration, which is limited by the doping solid solubility and the barrier height, which itself is determined by the choice of the metal. Known solutions for reducing interface resistivity include using rare earth metals, which have a reduced barrier height to a specific type of carrier, and dopant segregation techniques, which “pile up” dopants at the contact interface in order to increase the electric field at the contact interface, in turn reducing the contact barrier height. Since there is an upper limit to the dopant solubility and a lower limit to the achievable contact barrier height with dopant pile-up techniques (typically zero or near zero), there necessarily exists a lower limit to the interface resistivity. In addition, as the device pitch scales down, so does the contact area, which means that the interface resistivity must scale by at least the same amount in order to preserve the same percent-wise contribution of contact resistance to the total on-state resistance. Eventually, this will no longer be possible, due to the limitations mentioned above, at which point the contact resistance is expected to dominate the FET parasitic resistance. Therefore, due to the increased role that contact resistance plays in the total on-state resistance in aggressively scaled MOSFETs there is a corresponding need to minimize it.